|Table of Contents|

A Constant-Mobility Method to Extract Source/Drain ParasiticResistance for Nanometer CMOS Devices(PDF)

《南京师大学报(自然科学版)》[ISSN:1001-4616/CN:32-1239/N]

Issue:
2018年01期
Page:
50-
Research Field:
·物理学·
Publishing date:

Info

Title:
A Constant-Mobility Method to Extract Source/Drain ParasiticResistance for Nanometer CMOS Devices
Author(s):
Lu Mingliang1Tao Yongchun2
(1.School of Rail Transportation,Nanjing Technical Vocational College,Nanjing 210019,China)(2.School of Physics and Technology,Nanjing Normal University,Nanjing 210023,China)
Keywords:
nanometer CMOS devicessource/drain parasitic resistanceextraction method
PACS:
TN386.1
DOI:
10.3969/j.issn.1001-4616.2018.01.010
Abstract:
As a significant fraction of the total device resistance,source/drain parasitic resistance seriously limits the performance of deeply nanometer CMOS devices. The source/drain parasitic resistance is becoming a larger fraction of the total device resistance as the nanometer CMOS scales down. Therefore,it is a important parameter of reliability for CMOS devices. A source/drain parasitic resistance extraction method is proposed from the conditions in which the channel mobility remains constant. Source/drain parasitic resistance is extracted from the ratio of two linear Id-Vgs curves in the fixed bias conditions. This method avoiding the gate length dependent errors induced by mobility degradation in extraction procedures is simple and accurate. We specifically arrange the bias conditions in which the effect of vertical electrical filed on channel mobility is eliminated and the stability of the source/drain parasitic resistance is ensured. Under the suitable bias conditions,the source/drain parasitic resistances of different gate length under 45 nm technology is extracted,and it is independent with the gate length. Finally,the fluctuations of process and calculation are investigated and the errors are analyzed.

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Last Update: 2018-03-31