[1]鲁明亮,陶永春.一种提取纳米CMOS器件中源/漏寄生电阻的恒定迁移率方法[J].南京师范大学学报(自然科学版),2018,41(01):50.[doi:10.3969/j.issn.1001-4616.2018.01.010]
 Lu Mingliang,Tao Yongchun.A Constant-Mobility Method to Extract Source/Drain ParasiticResistance for Nanometer CMOS Devices[J].Journal of Nanjing Normal University(Natural Science Edition),2018,41(01):50.[doi:10.3969/j.issn.1001-4616.2018.01.010]
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一种提取纳米CMOS器件中源/漏寄生电阻的恒定迁移率方法()
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《南京师范大学学报》(自然科学版)[ISSN:1001-4616/CN:32-1239/N]

卷:
第41卷
期数:
2018年01期
页码:
50
栏目:
·物理学·
出版日期:
2018-03-31

文章信息/Info

Title:
A Constant-Mobility Method to Extract Source/Drain ParasiticResistance for Nanometer CMOS Devices
文章编号:
1001-4616(2018)01-0050-05
作者:
鲁明亮1陶永春2
(1.南京高等职业技术学校轨道交通学院,江苏 南京 210019)(2.南京师范大学物理科学与技术学院,江苏 南京 210023)
Author(s):
Lu Mingliang1Tao Yongchun2
(1.School of Rail Transportation,Nanjing Technical Vocational College,Nanjing 210019,China)(2.School of Physics and Technology,Nanjing Normal University,Nanjing 210023,China)
关键词:
纳米CMOS器件源/漏寄生电阻提取方法
Keywords:
nanometer CMOS devicessource/drain parasitic resistanceextraction method
分类号:
TN386.1
DOI:
10.3969/j.issn.1001-4616.2018.01.010
文献标志码:
A
摘要:
源/漏寄生电阻作为器件总电阻的一个重要组成部分,严重制约着纳米CMOS器件性能. 随着纳米CMOS器件尺寸不断减小,源/漏寄生电阻占器件总电阻比例越来越高,已经成为衡量CMOS器件可靠性的一个重要参数. 本文提出一种恒定沟道迁移率条件下提取纳米CMOS器件中源/漏寄生电阻的方法. 本方法通过测量固定偏压条件下一个器件的两条线性区Id-Vgs曲线之比,推导出纳米CMOS器件中源/漏寄生电阻,操作简单,精确度高,避免了推导过程中由沟道迁移率退化引入与器件栅长相关的误
Abstract:
As a significant fraction of the total device resistance,source/drain parasitic resistance seriously limits the performance of deeply nanometer CMOS devices. The source/drain parasitic resistance is becoming a larger fraction of the total device resistance as the nanometer CMOS scales down. Therefore,it is a important parameter of reliability for CMOS devices. A source/drain parasitic resistance extraction method is proposed from the conditions in which the channel mobility remains constant. Source/drain parasitic resistance is extracted from the ratio of two linear Id-Vgs curves in the fixed bias conditions. This method avoiding the gate length dependent errors induced by mobility degradation in extraction procedures is simple and accurate. We specifically arrange the bias conditions in which the effect of vertical electrical filed on channel mobility is eliminated and the stability of the source/drain parasitic resistance is ensured. Under the suitable bias conditions,the source/drain parasitic resistances of different gate length under 45 nm technology is extracted,and it is independent with the gate length. Finally,the fluctuations of process and calculation are investigated and the errors are analyzed.

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备注/Memo

备注/Memo:
收稿日期:2017-10-17.
基金项目:国家自然科学基金(10947005).
通讯联系人:鲁明亮,讲师,研究方向:理论物理学. E-mail:lml5127@126.com
更新日期/Last Update: 2018-03-31