[1]鲁明亮,陶永春.一种提取纳米CMOS器件中源/漏寄生电阻的恒定迁移率方法[J].南京师范大学学报(自然科学版),2018,41(01):50.[doi:10.3969/j.issn.1001-4616.2018.01.010]
　Lu Mingliang,Tao Yongchun.A Constant-Mobility Method to Extract Source/Drain ParasiticResistance for Nanometer CMOS Devices[J].Journal of Nanjing Normal University(Natural Science Edition),2018,41(01):50.[doi:10.3969/j.issn.1001-4616.2018.01.010]
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一种提取纳米CMOS器件中源/漏寄生电阻的恒定迁移率方法()
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《南京师范大学学报》（自然科学版）[ISSN:1001-4616/CN:32-1239/N]

卷:
第41卷
期数:
2018年01期
页码:
50
栏目:
·物理学·
出版日期:
2018-03-31

文章信息/Info

Title:
A Constant-Mobility Method to Extract Source/Drain ParasiticResistance for Nanometer CMOS Devices
文章编号:
1001-4616(2018)01-0050-05
作者:
鲁明亮1; 陶永春2
(1.南京高等职业技术学校轨道交通学院,江苏 南京 210019)(2.南京师范大学物理科学与技术学院,江苏 南京 210023)
Author(s):
Lu Mingliang1; Tao Yongchun2
(1.School of Rail Transportation,Nanjing Technical Vocational College,Nanjing 210019,China)(2.School of Physics and Technology,Nanjing Normal University,Nanjing 210023,China)
关键词:
纳米CMOS器件; 源/漏寄生电阻; 提取方法
Keywords:
nanometer CMOS devices; source/drain parasitic resistance; extraction method
分类号:
TN386.1
DOI:
10.3969/j.issn.1001-4616.2018.01.010
文献标志码:
A
摘要:
源/漏寄生电阻作为器件总电阻的一个重要组成部分,严重制约着纳米CMOS器件性能. 随着纳米CMOS器件尺寸不断减小,源/漏寄生电阻占器件总电阻比例越来越高,已经成为衡量CMOS器件可靠性的一个重要参数. 本文提出一种恒定沟道迁移率条件下提取纳米CMOS器件中源/漏寄生电阻的方法. 本方法通过测量固定偏压条件下一个器件的两条线性区Id-Vgs曲线之比,推导出纳米CMOS器件中源/漏寄生电阻,操作简单,精确度高,避免了推导过程中由沟道迁移率退化引入与器件栅长相关的误
Abstract:
As a significant fraction of the total device resistance,source/drain parasitic resistance seriously limits the performance of deeply nanometer CMOS devices. The source/drain parasitic resistance is becoming a larger fraction of the total device resistance as the nanometer CMOS scales down. Therefore,it is a important parameter of reliability for CMOS devices. A source/drain parasitic resistance extraction method is proposed from the conditions in which the channel mobility remains constant. Source/drain parasitic resistance is extracted from the ratio of two linear Id-Vgs curves in the fixed bias conditions. This method avoiding the gate length dependent errors induced by mobility degradation in extraction procedures is simple and accurate. We specifically arrange the bias conditions in which the effect of vertical electrical filed on channel mobility is eliminated and the stability of the source/drain parasitic resistance is ensured. Under the suitable bias conditions,the source/drain parasitic resistances of different gate length under 45 nm technology is extracted,and it is independent with the gate length. Finally,the fluctuations of process and calculation are investigated and the errors are analyzed.

参考文献/References:

[1] NG K K,LYNCH W T. Analysis of the gate-voltage-dependent series resistance of MOSFET’s[J]. IEEE transactions on electron devices,1986,33(7):965-972.
[2]KIM S D,PARK C M,WOO J C S. Advanced model and analysis of series resistance for CMOS scaling into nanometer regime. Ⅱ. Quantitative analysis[J]. IEEE transactions on electron devices,2002,49(3):467-472.
[3]ORTIZ C A,GARCíA SáNCHEZ F J,LIOU J J. An improved method for extracting the difference between the drain and source resistances in MOSFETs[J]. Solid-state electron,1996,39:419-421.
[4]GHIBAUDO G. New method for the extraction of MOSFET parameters[J]. Electron devices letters,1988,24(9):543-545.
[5]KUO J J Y,FAN M L,LEE W,et al. Source/drain series resistance induced feedback effect on drain current mismatch and its implication[C]//2013 International Symposium on VLSI Technology,Systems,and Applications(VLSI-TSA).Hsinchu,Taiwan,China:IEEE,2013:1-2.
[6]NAZAROV A N,FERAIN I,AKHAVAN N D,et al. Field-effect mobility extraction in nanowire field-effect transistors by combination of transfer characteristics and random telegraph noise measurements[J]. Applied physics letters,2011,99(7):073502.
[7]CRETU T,BOUTCHACHA,GHIBAUDO G,et al. New ratio method for effective channel length and threshold voltage extraction in MOS transistors[J]. IEEE Electron Device Lett,2001,37(11):717-719.
[8]van MEER H,HENSON K,LYU J H,et al. Limitation of shift-andratio based Leff extraction techniques for MOS transistors with halo or pocket implants[J]. IEEE Trans Electron Devices,2000,21(3):133-136.
[9]TERADA K,MUTA H. A new method to determine effective MOSFET channel length[J]. Jpn J Appl Phys,1979,18(5):953-959.
[10]CHERN J,CHANG P,MOTTA R,et al. A new method to determine MOSFET channel length[J]. IEEE Electron Dev Lett,1980,1:170-173.
[11]GARCIíA S F J,ORTIZ C A,LIOU J J. On the extraction of the source and drain series resistances of MOSFETs[J]. Microelectronics reliability,1999,39(8):1 173-1 184.
[12]OTTEN J A M,KLAASSEN F M. A novel technique to determine the gate and drain bias dependent series resistance in drain engineered MOSFETs using one single device[J]. IEEE Trans Electron Devices,1996,43(9):1 478-1 488.
[13]REYCHAUDHURI A,DEEN M J,KING M I H,et al. Finding the asymmetric parasitic source and drain resistances from the a.c. conductances of a single MOS transistor[J]. Solid-state electron,1996,39(6):909-913.
[14]LUCA S,ENRICO S,BRUNO R. Parameter extraction from I-V characteristics of single MOSFETs[J]. IEEE Trans Electron Device,1989,36(6):1 094-1 101.
[15]GUO J C,CHUNG S S,ANDHSU C C H. A new approach to determine the effective channel length and drain-and-source series resistance of miniaturized MOSFETs[J]. IEEE Trans Electron Devices,1994,41(10):1 811-1 818.
[16]FLEURY D,CROS A,BIDAL G,et al. A new technique to extract the source/drain series resistance of MOSFETs[J]. IEEE Electron Device Lett,2009,30(9):975-977.
[17]ADELMO O C,GARCíA S F J,JUAN M,et al. Indirect fitting procedure to separate the effects of mobility degradation and source-and-drain resistance in MOSFET parameter extraction[J]. Microelectronics reliability,2009,49(7):689-692.
[18]SELMI L,RICCO B. Frequency-resolved measurements for the characterization of MOSFET parameters at low longitudinal field[J]. IEEE Trans Electron Dev,1995,42:315-320.
[19]KIM Y C,KIM H T,CHO S D,et al. Extraction of device model parameters in MOSFETs by combining C-V and I-V characteristics[J]. Journal of the Korean physical society,2002,40(1):60-63.
[20]JUAN M,DENISE C L M,áLVARO D L R,et al. A new integration-based procedure to separately extract series resistance and mobility degradation in MOSFETs[J]. Semicond Sci Technol,2009,24(10):105015.
[21]FLEURY D,CROS A,BRUT H,et al. New Y-function-based methodology for accurate extraction of electrical parameters on nano-scaled MOSFETs[C]//2008 IEEE international conference on microelectronic test structures(ICMTS). Edinburgh,2008.
[22]BAEK R H,BAEK C K,JUNG S W,et al. Characteristics of the series resistance extracted from Si nanowire FETs using the Y-function technique[J]. IEEE Trans Nano Technol,2010,9:212-217.
[23]LIN D W,CHENG M L,WANG S W,et al. A Constant-mobility method to enable MOSFET series-resistance extraction[J]. IEEE electron device Lett,2007,28:1 132-1 134.
[24]HO C S,LO Y C,CHANG Y H,et al. Determination of gate-bias dependent source/drain series resistance and effective channel length for advanced MOS devices[J]. Solid-state electron,2006,50:1 774-1 779.
[25]MEIJER E J,GELINCK G H,Van VEENENDAAL E,et al. Scaling behavior and parasitic series resistance in disordered organic field-effect transistors[J]. Applied physics letters,2003,82(25):4 576-4 578.
[26]CHEN W P N,SU P,GOTO K I,et al. Series resistance and mobility extraction method in nanoscale MOSFETs[J]. J Electro Chem Soc,2009,156(1):H34-H38.
[27]CAMPBELL J P,CHEUNG K P,SUEHLE J S,et al. A simple series resistance extraction methodology for advanced CMOS devices[J]. IEEE electron device letters,2011,32(8):1 047-1 049.
[28]CAMPBELL J P,CHEUNG K P,DROZDOV S A,et al. Channel length-dependent series resistance?[C]//Silicon nanoelectronics workshop(SNW). Hawaii,USA:IEEE,2012:1-2.
[29]MA L J,JI X L,CHEN Y C,et al. Extraction of channel length independent series resistance for deeply scaled metal-oxide-semiconductor field-effect transistors[J]. Chinese physics letters,2014,31(9):097302.

备注/Memo

备注/Memo:
收稿日期:2017-10-17.
基金项目:国家自然科学基金(10947005).
通讯联系人:鲁明亮,讲师,研究方向:理论物理学. E-mail:lml5127@126.com
更新日期/Last Update: 2018-03-31